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Fujitsu Develops 90nm CMOS Technology for Digital Consumer and Mobile Applications
Unveils CS101 Series of System LSIs Built upon New Flexible SoC Platform
Tokyo, July 17, 2003 -- Fujitsu Limited today announced that is has developed and begun accepting orders for the CS101 Series of system-on-chips (SoCs) employing its state-of-the-art 90nm CMOS technology.
Fujitsu was among the first in the industry to deploy 90nm CMOS technology, starting production at its Akiruno Technology Center in December 2002. Fujitsu first used the technology in its own high-end products that demanded ultra-high speed performance. The new SoC platform builds on the expertise developed at the Akiruno Technology Center in 10-layer copper interconnects, Low-k insulating material, and other advanced technologies, making increased integration and reduced power consumption available for the SoC chips for digital consumer and mobile applications.
The CS101 Series achieves roughly double the level of integration of the company's existing CS91 Series of SoCs: up to 100 million gates, with the lowest power consumption in the industry, and a mere one-tenth the leakage current of the CS91 Series. All these make the new lineup especially well suited to mobile devices for which compactness and low power consumption are especially important.
With the adoption of Fujitsu's new SoC device, a mobile phone could offer six consecutive hours of talk-time and up to 1,000 hours of standby time, and a credit card-sized digital camera could be miniaturized even further.
Fujitsu has a strong production track record in advanced process technologies combining copper interconnects and Low-k insulating material for its last two generation of system devices, 0.13 m and 90nm. Based on this proven record of reliability, Fujitsu is now making these technologies available to implement in SoC chips for digital consumer and mobile applications.
In addition to offering increased integration and functionality, Fujitsu can help customers cope with the problem of long, complex design cycles with its DesignExpress™ short TAT service, which can slash the time and steps required in design by half.
Fujitsu plans to extend the CS101 series with the addition of a high-speed interface for use in networking equipment, and will roll out products for an expanded range of applications starting next year.
Sample Pricing and Availability
Price: Quoted individually
Custom design orders accepted as of July 17; sample shipments beginning September.
Main Product Features
- Low Power-Consumption Transistor Technology
Leakage current of transistor is held to the lowest levels in the industry, cutting standby power consumption to roughly one-tenth that found in the company's existing devices, the CS91 Series. When running at 1.2V, operating power consumption is 2.7 nW (at 1 gate, 1MHz), roughly half that of earlier devices.
- Advanced Process Technology for Increased Integration
With a density of 420,000 gates per square millimeter, this design can accommodate up to 100 million gates per chip, roughly double that of its predecessor. Each SRAM cell uses only 1.14 m2, among the smallest in the industry. Copper interconnects-up to ten layers of them-minimize resistance, and the use of Low-k insulating material across the entire chip for reduced interconnect capacitance helps to minimize the impact on electrical characteristics.
- Optimized Design with Three Types of Transistors Achieves Both Low Power Consumption and High Speed
Adopting a mixture of three different kinds of core transistors--low leakage current transistors, high-speed transistors, and ultra-high-speed transistors--enables the SoCs to achieve the twin goals of low power consumption and high speed. The gate delay time, which uses the high-speed transistors, is 12 picoseconds, about 70% faster than the CS91 Series of products.
- IP Macros for a Wide Range of Features
To support a wide range of applications, which may require A/D and D/A converters, PLLs, high-speed interfaces, low power consumption or high speeds, Fujitsu offers a range of fine-tuned macros.
- Fujitsu provides physical prototyping for this platform. By introducing this methodology, customers can reduce design time significantly. And with Fujitsu's short TAT service DesignExpress, customers can design FPGAs and ASICs concurrently, reducing design time and steps in half.
Main Product Specifications
Technology: Silicon-gate CMOS (gate length: 80 nm); 7-10 layer metal Interconnect; Low-k insulating material used throughout.
Power supply: 1.2V ± 0.1V internally
Raw gates: Up to 100 million
Gate delay: 12 ps (1.2V, inverter, fanout =1)
Gate power consumption: 2.7 nW (1gate, 1MHz)
Package: QFP, HQFP, EBGA, FBGA, PBGA, FC-BGA
Trademark notice
All product names and company names mentioned herein are the trademarks or registered trademarks of their respective firms.
About Fujitsu
Fujitsu is a leading provider of customer-focused IT and communications solutions for the global marketplace. Pace-setting technologies, highly reliable computing and telecommunications platforms, and a worldwide corps of systems and services experts uniquely position Fujitsu to deliver comprehensive solutions that open up infinite possibilities for its customers' success. Headquartered in Tokyo, Fujitsu Limited (TSE:6702) reported consolidated revenues of 4.6 trillion yen (US$38 billion) for the fiscal year ended March 31, 2003. For more information, please see : http://www.fujitsu.com/.
For more information on Fujitsu's Electronic Devices, please see http://edevice.fujitsu.com.
 Press Contacts
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[Customer Contacts]
LSI Group
ASIC, Network & Communication Products Div.
ASIC Marketing & Application Engineering Dept.
Tel: Tel: +81-44-754-2526
E-mail: edevice@fujitsu.com
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All company/product names mentioned may be trademarks or registered trademarks of their respective holders and are used for identification purpose only.
Please understand that product prices, specifications and other details are current on the day of issue of the press release, however, may change thereafter without notice.
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