|[ PRESS RELEASE ]
Fujitsu LSI Solutions Limited
Fujitsu Laboratories Ltd.
Fujitsu Develops CMOS Interface Technology
for 40Gbps Optical Communications Systems
Complies with OIF's SFI-5 Specification
Tokyo, December 26, 2002 - Fujitsu Limited, Fujitsu LSI Solutions Limited, and Fujitsu Laboratories Ltd. today announced their joint development of an interface device for next-generation high-bandwidth optical communications systems running at 40Gbps (40 billion bits per second). The interface technology, which complies with the Optical Internetworking Forum's (OIF)(*1) SFI-5 (*2) specification, is now being implemented in system-on-chip ASICs using Fujitsu's advanced 0.11 µm CMOS process technology.
As broadband Internet access grows more ubiquitous, bandwidth demands are expected to skyrocket. For that reason, 40Gbps optical communications systems using Dense Wave-Division Multiplexing (DWDM), which enables large volumes of data to be transmitted at ultra-high speed, are being developed around the world to accommodate this demand.
One component that 40Gbps optical communication systems need is an interface circuit between an optical module, which converts the 40Gbps optical stream to an electrical signal, and a signal-processing chipset. Because of the need for high-speed performance, until now interface circuits have been fabricated using silicon-germanium devices or other high-speed compound semiconductors. Interface circuits fabricated using CMOS process technology, however, would have the dual advantage of being easy to embed in system-on-chip ASICs while requiring very little power consumption. Fujitsu had already succeeded in developing a 3.125Gbps interface circuit using 0.18 µm standard CMOS process technology, and the development of a device with low power requirements that complies with the OIF's SFI-5 specification was awaited with much anticipation.
About the Technology
Fujitsu's new interface technology, featuring low-voltage CMOS high-speed analog circuit technology that is optimized for 0.11 µm CMOS processes, achieves ultra-high speed performance without requiring any additional special steps in the fabrication process.
Specifically, by reducing the output jitter in the low-voltage phase locked loop (PLL) (*3), Fujitsu was able to achieve transmission characteristics that comply with the SFI-5 specification. Moreover, by optimizing the circuit, Fujitsu succeeded in achieving dynamic phase alignment (DPA) (*4) performance that exceeds the minimum level called for in the specification.
Fujitsu's newly developed technology has the following key features:
- High speed, low power consumption
Transfers data at speeds up to 3.125Gbps per channel, with a 16-channel parallel interface to handle high data transfer rates of 40-50Gbps. CMOS process technology enables it to achieve the high-speed performance comparable to compound semiconductors while requiring no more than one-tenth of the power (about 1.5W sending + receiving total)
- Can be integrated into chips with 10 million+ gates
Use of Fujitsu's standard 0.11 µm CMOS process means that this design can be incorporated into a larger chip system (ASIC or ASSP).
- Complies with industry standards
This technology complies with the OIF's SFI-5 specification, ensuring that it is interoperable with the optical modules and signal-processing chips of other vendors.
- Scalable to 10Gbps systems
This interface is compatible with both 40Gbps and 10Gbps systems, so it works with customers' existing optical modules.
- *1. OIF
The Optical Internetworking Forum. A standards-setting industry organization of over 300 companies that manufacture high-speed optical systems and devices. See http://www.oiforum.com
- *2. SFI-5
SerDes Framer Interface Level 5. Defines the interface between the optical module and the signal-processing chip, or between two different signal-processing chips. This establishes 16 channels with 2.5-3.125Gbps per channel, for a total of 40-50Gbps of bandwidth.
- *3. PLL
Phase locked loop. Detects differences in the output frequency, the input, and the frequency of the standard oscillator. It controls the feedback circuit, and synchronizes the frequency of the oscillator.
- *4. DPA
Dynamic phase alignment. A method for sampling data that automatically aligns the clock phase with the data phase.
All product names and company names mentioned herein are the trademarks or registered trademarks of their respective firms.
Fujitsu is a leading provider of customer-focused IT and communications solutions for the global marketplace. Pace-setting technologies, high-reliability/performance computing and telecommunications platforms, and a worldwide corps of systems and services experts make Fujitsu uniquely positioned to unleash the infinite possibilities of the broadband Internet to help its customers succeed. Headquartered in Tokyo, Fujitsu Limited (TSE:6702) reported consolidated revenues of 5 trillion yen (about US$38 billion) for the fiscal year ended March 31, 2002. For more information, please see: http://www.fujitsu.com/
Chiaki Kuwahara, Nancy Ikehara
Fujitsu LimitedPublic & Investor Relations
Tel: +81-3-3215-5259 (Tokyo)
Network & Communication Products Dept.
ASIC, Network & Communication Products Div.
All company/product names mentioned may be trademarks or registered trademarks of their respective holders and are used for identification purpose only.
Please understand that product prices, specifications and other details are current on the day of issue of the press release, however, may change thereafter without notice.