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Fujitsu Unveils World's First High-Performance Embedded Multimedia Processor with Simultaneous Eight-Instruction Execution Capability
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Fujitsu Unveils World's First High-Performance Embedded Multimedia Processor with Simultaneous Eight-Instruction Execution Capability

Tokyo, February 13, 2002--Fujitsu Laboratories Ltd. and Fujitsu Limited announced the development of a new high-performance multimedia processor for embedded applications, the world's first to execute eight instructions in parallel. At a clock speed of 533 MHz, this chip is capable of 12.8 GOPS (about 12.8 billion iterations per second), providing the kind of processing power needed to handle video and other types of media processing.

The new processor is compatible with Fujitsu's existing FR-V family*1 of chips based on very long instruction word (VLIW)*2 architecture and will be positioned at the high-end of the FR-V line as the FR550, which is slated to go into mass production later this year.

The new chip was unveiled this month at the ISSCC2002 (the 2002 IEEE International Solid-State Circuits Conference).

As printers, mobile devices, digital cameras, car-navigation systems and other electronic equipment are equipped with increasingly advanced functions, they need to be able to handle high-speed processing of large volumes of data, such as high-resolution images. Ordinary embedded processors simply are not up to the task, so custom ASICs are typically used, but these take time to develop and still may not provide the desired level of processing power.

To address these problems, in 2000, Fujitsu introduced the high-performance embedded processor, the FR500. Now Fujitsu has developed an even more powerful processor for more advanced data-handling capabilities.

About the Technology
Successor to the FR500, the new processor is based on VLIW technology, which allows simultaneous execution of a unit dedicated to multimedia processing and a general-purpose processing unit. In addition to doubling the number of calculation sub-units that simultaneously operate within each unit, the chip includes a dynamic branch-prediction function and new load-store method.

The new processor achieves a 40% performance increase over the FR500 at a given clock speed, and is also capable of running at clock speeds up to 50% higher than its predecessor. In actual terms, JPEG*3 processing (which compresses and decompresses still color images) is at least 2.5 times faster (based on estimates from Fujitsu Laboratories). And because the new chip retains compatibility with the four-way parallel VLIW FR500, programs for the old chip will run on the new one without modification.

The new processor has the following three noteworthy features:

  1. Significantly higher calculating speed
    The FR550 doubles the number of instructions that can be executed simultaneously from the FR500's four to eight. It achieves this by executing four ordinary instructions at the same time that it executes four floating-point or multimedia instructions, resulting in a dramatic improvement in calculating speed. The multiport register file that makes this possible is also being presented at ISSCC2002.

  2. Active branch-prediction
    The FR500 and FR400 both use passive branch-prediction, whereby commands for the direction to take in branching instructions came from software. By contrast, the new processor uses active branch-prediction, whereby commands are automatically handled at the hardware level. This feature helps reduce branch-related interlocks and improves performance.

  3. New load/store method optimized for dealing with multimedia data
    To boost memory-access performance to the level needed for dealing with signal data, the onboard cache has been doubled to 32 KB. In addition, the store operation, which previously could only be executed once per cycle, can now be executed twice per cycle for a significant boost in memory-access performance.

To meet the key requirement of all embedded processors for low power consumption, Fujitsu manufactures this chip using a cutting-edge 0.11 µm metal CMOS process.

Technology0.11 µm metal CMOS, 7-layer
Chip size7.8 x 7.8 mm
Transistor count10.4 million
Clock speed533 MHz
Power consumption2.5 W
PackagingPlastic BGA, 352 pins
Peak performance12.8 GOPS

*1. FR-V Family
Fujitsu's newest series of high-performance processors using VLIW architecture. Fujitsu's previous series include the 4-way parallel VLIW architecture FR500 Series released in July 1999, followed by the 2-way parallel VLIW architecture FR400 Series, with a lower price and lower power consumption, released in March 2001.

*2. Very long instruction word (VLIW):
As the name implies, this is a processor architecture where a single instruction is very long (96-, 128-, or 256-bits), and each instruction in fact encapsulates multiple processes that are executed simultaneously.

*3. JPEG (Joint Photographic Expert Group):
A compressed format for still color images.

About Fujitsu Laboratories Ltd.
Founded in 1968 as a wholly owned subsidiary of Fujitsu Limited, Fujitsu Laboratories Limited is one of the premier research centers in the world. With a global network of laboratories in Japan, China, the United States and Europe, the organization conducts a wide range of basic and applied research in the areas of Multimedia, Personal Systems, Networks, Peripherals, Advanced Materials and Electronic Devices. Internet:

About Fujitsu
Fujitsu is a leading provider of Internet-focused information technology solutions for the global marketplace. Its pace-setting technologies, best-in-class computing and telecommunications platforms, and worldwide corps of systems and services experts make it uniquely positioned to unleash the infinite possibilities of the Internet to help its customers succeed. Headquartered in Tokyo, Fujitsu Limited (TSE:6702) reported consolidated revenues of 5.48 trillion yen for the fiscal year ended March 31, 2001. Internet:

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[Press Contacts]
Minoru Sekiguchi, Nancy Ikehara
Fujitsu Limited, Public Relations
Tel: +81-3-3215-5259 (Tokyo)
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Fujitsu Laboratories
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