Fujitsu Laboratories Ltd. Fujitsu Laboratories of America, Inc. Fujitsu Limited

Tokyo, February 7, 2002 - Fujitsu Laboratories Ltd., Fujitsu Laboratories of America, Inc. and Fujitsu Limited today announced the development of a multiport register file*1 technology that can meet the high performance, low power consumption and minimal space requirements of system-on-chip designs. Use of this technology will facilitate a quicker and less costly design process, resulting in more powerful chips. The technology has already been used in Fujitsu's FR-V*2 series of 8-way parallel high-performance multimedia processors.

The multiport register file, which takes up less chip space than earlier register file technology, can achieve 1.4 ns access time running on 220 mW of power (at 500 MHz) in performance mode, or 3.9 ns access time running on 28 mW (at 200 MHz) in energy-saving mode. This development was announced this month at the ISSCC2002 (the 2002 IEEE International Solid-State Circuits Conference).

Background
Over the past few years, very long instruction word (VLIW)*3 and superscalar*4 processors have been developed to increase the number of instructions that can be issued in a single clock cycle. These developments have made the need for multiport register files more pressing, as they permit more efficient use of the calculating units on these processors by reading/writing more data during one clock cycle. The indispensable features for multiport register files are high performance and low power consumption. In addition, since space requirements tend to increase with the number of ports, it is very important to minimize the amount of area required on the chip for the multiport register files.

Notable Features of the Technology
Fujitsu's new multiport register file technology includes 10 read and six write ports, storing 34 words of 64 bits. The technology, which is designed to meet high performance, low power consumption and minimal space requirements, has three notable features.

First, the technology supports two different power modes of operation. With two different power sources, this technology can run in performance mode or energy-saving mode by changing the power source and driver voltage. A replica circuit*5 in the design enables it to operate across a wide range of voltages.

Second, single-rail bit lines*6 reduce space requirements by almost one third. A layout of bit-lines and shield-lines using single-rail bit lines enables typical noise tolerances to be maintained with only half the overall number of bit-lines required. As a result, circuit area space requirements are reduced by 31 percent.

Finally, a write-through read function makes for faster performance and simpler circuit design. This function, which reads data on the same cycle as data is being written, simplifies circuit design and improves performance.

Major Specifications
This macro uses Fujitsu's leading-edge 0.11 µm metal CMOS process.

Technology	0.11 µm CMOS 4-layer metal
Configuration	34 words x 64 bits10 read ports6 write ports
Macro size	1 mm x 0.5 mm (31% smaller than typical)
Operating clock rate	545 MHz @ 1.2 V Vdd
Power consumption	220 mW @ 500 MHz (performance mode)
Access time	1.4 ns @ 1.2 V Vdd (performance mode)

Glossary

1. Register file

A type of low-capacity, high-speed memory. Runs at the processor's maximum clock rate, and typically permits data to be read and written in one clock cycle.

2. FR-V

Fujitsu's newest series of high-performance processors using VLIW architecture. Previous series include the four-way parallel VLIW architecture FR500 Series released in June 2000, followed by the two-way parallel VLIW architecture FR400 Series, with a lower price and lower power consumption, released in March 2001.

3. Very long instruction word (VLIW)

As the name implies, this is a processor architecture where a single instruction is very long (normally 128 bits or more), and each instruction in fact encapsulates multiple processes that are executed simultaneously.

4. Superscalar

A processor architecture where multiple instructions are executed during a single clock cycle, where the processor can, by itself, control the order of execution for instructions.

5. Replica circuit

A circuit model with an architecture partly identical to a circuit in actual use. This feature enables stable operation of the circuit under variable power-supply voltages, process conditions and temperatures, by accommodating fluctuations in the timing signal that result from these variations.

6. Single-rail bit-line

Uses only a single line for each read and write data port.

About Fujitsu Laboratories Ltd.
Founded in 1968 as a wholly owned subsidiary of Fujitsu Limited, Fujitsu Laboratories Limited is one of the premier research centers in the world. With a global network of laboratories in Japan, China, the United States and Europe, the organization conducts a wide range of basic and applied research in the areas of Multimedia, Personal Systems, Networks, Peripherals, Advanced Materials and Electronic Devices. Internet: http://www.labs.fujitsu.com/en/

About Fujitsu
Fujitsu is a leading provider of Internet-focused information technology solutions for the global marketplace. Its pace-setting technologies, best-in-class computing and telecommunications platforms, and worldwide corps of systems and services experts make it uniquely positioned to unleash the infinite possibilities of the Internet to help its customers succeed. Headquartered in Tokyo, Fujitsu Limited (TSE:6702) reported consolidated revenues of 5.48 trillion yen for the fiscal year ended March 31, 2001. Internet: http://www.fujitsu.com/

[Press Contacts] Minoru Sekiguchi, Nancy Ikehara Fujitsu Limited, Public Relations Tel: +81-3-3215-5259 (Tokyo) Fax: +81-3-3216-9365 Press Inquiries

[Customer Contact] System LSI Development Lab Fujitsu Laboratories Tel: +81-44-754-2657 (Kawasaki) E-mail: inoue.atsuki@jp.fujitsu.com

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